RISC-V

Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5

Divyansh Agrawal compiles a RISC-V CPU directly into the weights of a stock Qwen 3.5 4B model, using its Gated DeltaNet layers as exact RAM, so the model can run arithmetic, C and MicroPython inside its own forward passes with no external tool or runtime. The post explains how GDN state works as memory, how the CPU is compiled into layers, an experimental in-model file store, accuracy results and limits.

Research · LLMs · Machine Learning · AI Research · RISC-V