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How to run a city builder on 16 MHz
A look at how the original SimCity ran a full city simulation on a 16 MHz 386SX: its Simulate() function only runs a slice of the systems each frame, a frame-distribution trick that also shows up in Assetto Corsa's cubemap reflections and Unreal's Lumen lighting.
4 min · 998 words
Cache-to-Cache: Direct Semantic Communication Between Large Language Models
Fu et al. propose Cache-to-Cache (C2C): multi-LLM systems exchange KV-cache semantics directly instead of text tokens, aiming for richer inter-model communication with lower latency and token cost.
52 min · 12,056 words
Matt Keeter writes a hand-tuned AArch64 assembly interpreter for the Uxn virtual machine and finds it about 30 percent faster than his safe-Rust baseline, explaining why dispatch dominates interpreter time, how keeping VM state in registers and per-opcode dispatch help, and follow-up experiments from readers.
16 min · 3,656 words
Surpassing 10Gb/s over TailscaleOriginal article link with an AI-written directory summary
Jordan Whited explains throughput improvements in Tailscale's userspace networking. The technical account explores UDP segmentation offload and checksum optimizations, with measurements showing how the changes affect Linux performance.
1 min · 74 wordsagent-written
The container throttling problemOriginal article link with an AI-written directory summary
Dan Luu and David Mackey examine why CPU-bound services can suffer severe performance degradation well below their reserved container capacity. The article connects Linux scheduling and CPU quotas with real service behavior.
1 min · 94 wordsagent-written
Some latency measurement pitfallsOriginal article link with an AI-written directory summary
A talk-derived explanation of ways latency dashboards can mislead service owners. Dan Luu examines missing instrumentation, aggregation limits, and coarse time resolution in measurements of distributed systems.
1 min · 74 wordsagent-written
Alex Kladov (matklad) argues that swapping std's Mutex for a spinlock to add no_std support in Rust crates is an anti-pattern, walking through how spinlocks work, priority inversion, CPU interrupts and why a spinning lock can deadlock, and proposes alternatives such as panicking when blocking is impossible.
9 min · 2,000 words
A practical guide to writing C++ that actually uses the machine well—covering language and hardware basics, common pitfalls, and habits that keep hot paths fast without premature micro-optimization theater.
17 min · 3,904 words
Gallery of Processor Cache Effects
Igor Ostrovsky's classic 2010 post uses short C# code samples to illustrate how processor caches shape real program performance: memory access patterns, cache lines, L1 and L2 sizes, instruction-level parallelism, cache associativity, false sharing of cache lines, and hardware quirks that are hard to explain.
12 min · 2,685 words