One CPU Atomic Instruction, One Packaging Infinite Loop: The Story of the Lost Update on LA664

Jie Ge documents a Loongson LA664 erratum where an atomic instruction can lose updates, how it surfaced as an infinite packaging loop, the root cause analysis, and what it means for correctness on that CPU.

Research · Hardware · Systems Programming · Debugging · Engineering

The Economics of Open-Weight Inference

How open-weight demand can support the useful life of NVIDIA GPU families. Selected figures and tables, limitations, and the full PDF.

Research · Economics · LLMs · Infrastructure · Hardware

Getting 50 GB/s Back Out of the ANE

Eileen Yoon identifies an RTL performance bug in the Apple M3 Neural Engine where DRAM throughput collapses from 45–60 GB/s to 17–19 GB/s whenever total weight size is an exact multiple of 1 MiB. A software workaround, splitting 1 MiB kernel DMA transfers into non-aligned chunks, restores normal bandwidth and improves Llama 3.2 1B token throughput from 10 to 24 tokens per second.

Research · Apple Silicon · Neural Engine · Performance · Hardware

Semantics for 2D Rasterization

Kulkarni, Whiting, and Panchekha introduce μSkia—a Lean-mechanized formal semantics for Skia 2D graphics—and an optimizer that speeds rasterization ~18.7% on Chrome-derived Skia programs while proving replacements correct.

Research · Research · Performance · Programming · Hardware